1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
Generally, semiconductor devices are categorized into lateral semiconductor devices, which have an electrode on one surface, and vertical semiconductor devices, which have an electrode on both surfaces. Vertical semiconductor devices are such that the direction in which a drift current flows when in an on-state and the direction in which a depletion layer caused by reverse bias voltage extends when in an off-state are the same. For example, an n-channel vertical MOSFET (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) with a normal planar gate structure is such that, when in an on-state, a portion of a high-resistance n− type drift layer functions as a region that causes drift current to flow in a vertical direction. Consequently, as drift resistance is lowered by shortening the current path of the n− type drift layer, an advantage is obtained in that it is possible to lower the practical on-state resistance of the MOSFET.
Meanwhile, a portion of the high-resistance n− type drift layer depletes when in an off-state, increasing breakdown voltage. Consequently, when the n− type drift layer is thinner, the spread of a drain-to-base depletion layer advancing from a p-n junction between a p-type base region and the n− type drift layer is reduced, and the critical electrical field strength of the silicon is quickly reached, because of which breakdown voltage drops. Conversely, a semiconductor device with high breakdown voltage is such that the n− type drift layer is thick, because of which the on-state resistance increases, and loss increases. In this way, there is a trade-off relationship between on-state resistance and breakdown voltage.
It is known that this trade-off relationship is also established in the same way in a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), bipolar transistor, or diode. Also, trade-off relationship is also common to lateral semiconductor devices, wherein the direction in which a drift current flows when in an on-state and the direction in which a depletion layer caused by reverse bias extends when in an off-state are different.
A superjunction semiconductor device wherein the drift layer is a parallel p-n structure, of a configuration wherein n-type drift regions with increased impurity concentration and p-type isolation regions are alternately and repeatedly joined, is commonly known as a method of resolving the problem of the trade-off relationship. See, for example, U.S. Pat. No. 5,216,275 (also referred to herein as “PTL 1”), U.S. Pat. No. 5,438,215 (also referred to herein as “PTL 2”) and Japanese Patent Application Publication No. JP-A-9-266311 (also referred to herein as “PTL 3”). A semiconductor device with this kind of structure is such that, even when the impurity concentration of the parallel p-n structure is high, a depletion layer spreads laterally from each vertically extending p-n junction of the parallel p-n structure when in an off-state, depleting the whole of the drift layer, because of which it is possible to achieve an increase in breakdown voltage.
Meanwhile, in the case of a semiconductor device including a diode, or a circuit utilizing a parastic diode incorporated in a MOSFET or the like, as with a bridge circuit, it is necessary to ensure that the device is not destroyed even when high di/dt occurs during a diode reverse recovery process. Increasing breakdown withstand by shortening the carrier lifetime of an edge termination region parallel p-n structure in comparison with the carrier lifetime of an active region parallel p-n structure, thereby reducing the current flowing from the edge termination region toward the active region, has been proposed as a method of resolving this kind of problem. See, for example, Japanese Patent Application Publication No. JP-A-2003-224273 (also referred to herein as “PTL 4”), Japanese Patent Application Publication No. JP-A-2004-22716 (also referred to herein as “PTL 5”), Japanese Patent No. 4,743,447 (also referred to herein as “PTL 6”) and Japanese Patent No. 3,925,319 (also referred to herein as “PTL 7”). In PTL 6, there is a description of integrating a diode and MOSFET, but there is no description of forming a p-type region in a drain region opposing an edge termination region of the MOSFET.
A description will be given of the configuration of an existing superjunction MOSFET to which localized lifetime technology is applied in this way. FIG. 5 is a sectional view showing the structure of an existing vertical MOSFET. FIG. 5 is FIG. 12 of PTL 5. As shown in FIG. 5, a drain drift portion 102 of a first parallel p-n structure is provided on a low-resistance n+ type drain layer 101 with which a back side drain electrode 113 is in contact electrically. A p-type base region 103 with a high impurity concentration, forming an active region 121, is selectively provided in a surface layer of the drain drift portion 102.
The drain drift portion 102 is a first parallel p-n structure, roughly corresponding to a portion directly below the multiple wells of the p-type base region 103 forming the active region 121, formed by layer form vertical first n-type regions 102a oriented in the thickness direction of the substrate and layer form vertical first p-type regions 102b oriented in the thickness direction of the substrate being alternately and repeatedly joined in a direction along the surface of the substrate at a repetition pitch P101. A MOS gate (an insulated gate formed of metal-oxide-semiconductor) structure formed of the p-type base region 103, a p+ type contact region 105, n+ type source region 106, gate dielectric 107, and gate electrode layer 108, and a source electrode 110, are provided on the substrate front surface side of the first parallel p-n structure. Reference sign 109 is an interlayer dielectric.
The periphery of the drain drift portion 102 is an edge termination region 122 formed of a second parallel p-n structure. The edge termination region 122 is contiguous with the first parallel p-n structure of the drain drift portion 102, and is formed by layer form vertical second n-type regions 112a oriented in the thickness direction of the substrate and layer form vertical second p-type regions 112b oriented in the thickness direction of the substrate being alternately and repeatedly joined in a direction along the surface of the substrate at the repetition pitch P101. The first parallel p-n structure and second parallel p-n structure are such that the repetition pitch P101 is practically the same, and the impurity concentration is also practically the same.
An oxide film 115 is provided on a surface of the second parallel p-n structure. A field plate electrode FP extended from the source electrode 110 is formed on the oxide film 115, covering the second parallel p-n structure. An n-type channel stopper region 114 connected to an n+ type drain layer 101 is formed on the exterior of the edge termination region 122, and a stopper electrode 116 is in contact electrically with the n-type channel stopper region 114. The second parallel p-n structure and n-type channel stopper region 114 are regions with a carrier lifetime shorter than that of the first parallel p-n structure.
However, in PTL 4 to 7, the amount of carriers accumulated in the edge termination region 122 is reduced by the carrier lifetime of the second parallel p-n structure of the edge termination region 122 being shortened in comparison with the carrier lifetime of the first parallel p-n structure of the active region 121, thereby increasing breakdown withstand with respect to a localized concentration of reverse recovery current during a reverse recovery process of a parasitic diode formed of the first p-type regions 102b and first n-type regions 102a, but there is a problem in that the leakage current when in an off-state increases due to the carrier lifetime of the second parallel p-n structure of the edge termination region 122 being shortened, as a result of which loss increases. Also, there is a problem in that when the leakage current in an off-state increases too far, the device is destroyed by thermal runaway.